描述

MOOG D138-002-002

采用該特性能幫助想進行時序仿真的設計師解決他們面臨的兩個最大難題：1)各個模塊重復使用測試基準的能力；2)定位發(fā)生問題的具體模塊的能力。可有多種途徑進行時序仿真。當采用MHF時，因為所有這些模塊的頂層端口都保持一致，所以可容易地重復使用RTL測試基準。

　　以組塊形態(tài)形成的最終網絡表確實可使用戶為其RTL等價物選取不同的模塊。這樣做，用戶將可加快模擬的運行時間。RTL幾乎永遠比結構化網絡表等快得多，若有種方法在不影響設計功能的前提下可用RTL替換結構碼，則就應嘗試這種方法。幾乎沒一種設計在實現后就盡善盡美。這就是為什么需要進行時序仿真的原因。

　　采用上述同一個例子，我們可考察如何改進整個設計的速度及可觀察性。為得到最短的運行時間，理想的情況是在一個模塊上一次僅運行時序仿真。此例中，我們可在子模塊A運行時序仿真然后使子模塊B、C和D處在RTL形式。一旦我們進行時序仿真并發(fā)現一切如預期的一樣，就可對任何子模塊進行切換并以相同的方式進行測試。采用該方法論還意味著，若在一個子模塊中發(fā)現了問題，則可容易地定位該問題子模塊并將它拿給該模塊的設計者進行修改。若發(fā)現多個子模塊存在問題，則該方法帶來的額外好處是，兩(多)個不同工程團隊能同時著手解決發(fā)現的問題。

　　在傳統流程中，當發(fā)現設計的一個部分存在問題時，只有在該部分的問題被解決后，設計師才可能處理設計的其它部分。在采用MHF設計流后將不再受這種限制。時序仿真用戶的另一個主要抱怨是：若其它工程團隊不在國內，則完成最后的驗證會相當困難且需花很長時間。這是因為，它將浪費許多時間以及當采用傳統時序仿真方法論時的許多相互關聯和依賴問題。借助MHF方法論，去掉了關聯因素。利用MHF，不同工程團隊可省去許多空閑時間。這將確保發(fā)揮團隊的最大效率。具有模塊結構的網絡表也能為驗證小組提供幫助。過去，需要由一位驗證工程師完成的工作現可由不同小組的多位驗證工程師完成。開發(fā)小組采用的理念也可同樣用于驗證小組。

　　除在模擬領域取得持續(xù)進展以外，在施加激勵的方法方面也有重要進步。過去的設計通常非常小，所以以前的設計激勵方法是采用模擬器提示(prompt)的施力文件(force file)或簡單刺激以切換每個信號。隨著設計變得益發(fā)復雜，施加激勵也需要更好的方法。這里，VHDL和Verilog 的能力將有用武之地。隨著HDL編碼語言的引入，測試基準變得更復雜和緊湊。

　　在該領域，出現了諸如PSL、SystemC和SystemVerilog等技術。這些語言覆蓋的范圍不在本文討論之內。這些編程方式的一個不利方面是它要求將一個模擬的輸出作為另一個模擬的輸入。一些模擬器支持允許用戶準確進行這種操控的Extended Value Change Dump Format 格式。不采用這種方法進行時序仿真的用戶遇到的主要障礙是：因為當將一切都展開后端口名稱將改變，所以沒辦法將輸出作為激勵。采用MHF方法會去掉此問題，因為，現在這里有可施以激勵的獨立模塊，另外，現在一個模塊的輸出可被用作另一個模塊進行RTL以及時序仿真的激勵。

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MOOG D138-002-002

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